Property:Current TRL

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Pages using the property "Current TRL"

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BB24.I +	9 for Semantic Technologies <br /> 9 for ABAC<br /> 2-4 for S-ABAC.  +
BB24.J +	TRL 5. FEV Advanced Controller and HMI (FACH). This platform is designed to handle various tasks related to automation, measurement and control tasks.  +
BB24.K +	Single components for this building block from DEWI are available on on TRL 5.  +
BB24.L +	5 for SDN and NFV<br /> 9 for cloud technologies<br /> 5 for consumer device technologies  +
BB25.A +	4  +
BB25.B +	TRL 3  +
BB25.C +	4  +
BB25.D +	TRL 3 (some laboratory experiments have taken place and the results have been published in technical reports)  +
BB25.E +	4  +
BB25.F +	2  +
BB25.G +	The current TRL for this Building Block (1-9) is TRL 2 – technology concept formulated.  +
BB26.A +	TRL 4 (This TRL value is justified by research tasks performed in the DEWI project. In this Building Block, different software components designed in DEWI will be integrated and adapted to the new functionality)  +
BB26.B +	Current TRL is 6  +
BB26.C +	TRL 3 . It is justified since the proposed smart router is taking advantage of the SW/HW functionalities providing QoS capabilities developed in the frame of the DEWI project and validated at laboratory environment. On the other hand, the same HW platform (a certified railway computer) will be reused for implementing the new functionalities related to smart routing features. However, the smart routing features (SW) are still a simulated concept (i.e. IP dynamic routing policies AND data link status monitoring info) and they are pending to be designed and implemented (and integrated with the QoS features) in a HW prototype.  +
BB26.D +	TRL 3  +
BB26.E +	TRL 2  +
BB26.F +	TRL 4  +
BB26.G +	TRL 1-2 for the ideas of Privacy Labels  +
BB26.H +	TRL 3  +
BB26.I +	TRL 3  +
BB26.J +	TRL-3. It is justified due to , on one hand, the proposed M2M waveform design was consolidated by mean of SW simulation model (i.e.transmitter and receiver are simulated at bit/sample level), using MATLAB and on the other hand, the receiver component was already implemented in a receiver front-end HW prototype (i.e bread-board) and subsequently validated in a real-time satcom network simulator.  +

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